SpyDrNet-Physical Documentation

SpyDrNet is a flexible framework for analyzing and transforming structural Verilog netlists. It allows users to design a complete structural Verilog netlist using python scripting or parser an existing Verilog netlist. The structural Verilog netlist is represented as a python class that simplifies the netlist modification process. The SpyDrNet is purely designed as a python package, keeping scalability in mind. In SpyDrNet-Physical is an extension for a SpyDrNet framework, which adds functionality to perform physical design-related netlist transformations.

Essential characteristics of a SpyDrNet-Physical

• Appends features like create_feedthrough, create_feedthrough_multiple, merge_instance which are important during netlist restructuring for physical design

• Includes some html and graph-based visualization features

• Only supports Verilog netlist, no support for EDIF or any other formats

Table of Contents

Users Content

• Install
• Tutorial
• API Reference
• Verilog Language Support
• Sample verilog netlist
• Physical Design for 4x4 FPGA
• Examples

Developeres Content

• Developers Guidelines
• Regression Tests

Indices and tables

• Index

• Module Index

• Search Page