.. DO NOT EDIT. .. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY. .. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE: .. "auto_basic/10_combine_wires.py" .. LINE NUMBERS ARE GIVEN BELOW. .. only:: html .. note:: :class: sphx-glr-download-link-note :ref:`Go to the end ` to download the full example code. .. rst-class:: sphx-glr-example-title .. _sphx_glr_auto_basic_10_combine_wires.py: ========================= Combined independent nets ========================= This example combines independent nets of the module to a single multipin cable (Bux) **Initial Design** .. image:: ../auto_sample_verilog/basic_hierarchy.svg :align: center .. GENERATED FROM PYTHON SOURCE LINES 15-22 .. code-block:: Python from os import path import spydrnet as sdn import spydrnet_physical as sdnphy # TODO print("NotImplemented") .. _sphx_glr_download_auto_basic_10_combine_wires.py: .. only:: html .. container:: sphx-glr-footer sphx-glr-footer-example .. container:: sphx-glr-download sphx-glr-download-jupyter :download:`Download Jupyter notebook: 10_combine_wires.ipynb <10_combine_wires.ipynb>` .. container:: sphx-glr-download sphx-glr-download-python :download:`Download Python source code: 10_combine_wires.py <10_combine_wires.py>` .. container:: sphx-glr-download sphx-glr-download-zip :download:`Download zipped: 10_combine_wires.zip <10_combine_wires.zip>` .. only:: html .. rst-class:: sphx-glr-signature `Gallery generated by Sphinx-Gallery `_