.. DO NOT EDIT.
.. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY.
.. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE:
.. "auto_openfpga_basic/10_optimize_pins.py"
.. LINE NUMBERS ARE GIVEN BELOW.

.. only:: html

    .. note::
        :class: sphx-glr-download-link-note

        :ref:`Go to the end <sphx_glr_download_auto_openfpga_basic_10_optimize_pins.py>`
        to download the full example code.

.. rst-class:: sphx-glr-example-title

.. _sphx_glr_auto_openfpga_basic_10_optimize_pins.py:


======================
Optimizing module pins
======================
This example demonstrate how to optimize the module pins based on the
connectivity of the current instances.


**Before Optimization**

.. image:: ../../../examples/OpenFPGA_basic/_simple_design.svg
   :width: 60%
   :align: center

**After Optimization**

.. image:: ../../../examples/OpenFPGA_basic/_simple_design_post_opt_pins.svg
   :width: 60%
   :align: center

.. GENERATED FROM PYTHON SOURCE LINES 22-31

.. code-block:: Python


    import logging

    import spydrnet as sdn
    from spydrnet_physical.composers.svg.composer import SVGComposer

    logger = logging.getLogger('spydrnet_logs')
    sdn.enable_file_logging(LOG_LEVEL="DEBUG", filename="pin_opt")


.. GENERATED FROM PYTHON SOURCE LINES 32-36

Example 1
~~~~~~~~~



.. GENERATED FROM PYTHON SOURCE LINES 37-104

.. code-block:: Python



    with open("_simple_design.v", "w", encoding="UTF-8") as fp:
        fp.write('''
        module top(in0, out);
            input in0;
            output [1:0]out;

            block1 instance1 (.in0(in0), .in1(in0), .out(out[0]));
            block1 instance2 (.in0(in0), .in1(in0), .out(out[1]));

        endmodule

        `celldefine
        module block1(in0, in1, out);
            input in0;
            input in1;
            output out;

        endmodule
        `endcelldefine
        ''')


    with open("_simple_design.v", "w", encoding="UTF-8") as fp:
        fp.write('''
        module top(in0, out);
            input in0;
            output out;

            wire mid_out;

            block1 instance1 (.in0(in0), .in1(mid_out), .out(out));
            block2 instance2 (.in0(in0), .in1(mid_out), .in3(mid_out), .out(mid_out));

        endmodule

        `celldefine
        module block1(in0, in1, out);
            input in0;
            input in1;
            output out;

        endmodule
        `endcelldefine

        `celldefine
        module block2(in0, in1, in3, out);
            input in0;
            input in1;
            input in3;
            output out;

        endmodule
        `endcelldefine
        ''')

    netlist = sdn.parse("_simple_design.v")

    composer = SVGComposer()
    composer.run(netlist, file_out="_simple_design.svg")

    next(netlist.get_definitions("block2")).OptPins()

    composer = SVGComposer()
    composer.run(netlist, file_out="_simple_design_post_opt_pins.svg")
    sdn.compose(netlist, '_simple_design_post_opt_pins.v', skip_constraints=True)


.. _sphx_glr_download_auto_openfpga_basic_10_optimize_pins.py:

.. only:: html

  .. container:: sphx-glr-footer sphx-glr-footer-example

    .. container:: sphx-glr-download sphx-glr-download-jupyter

      :download:`Download Jupyter notebook: 10_optimize_pins.ipynb <10_optimize_pins.ipynb>`

    .. container:: sphx-glr-download sphx-glr-download-python

      :download:`Download Python source code: 10_optimize_pins.py <10_optimize_pins.py>`

    .. container:: sphx-glr-download sphx-glr-download-zip

      :download:`Download zipped: 10_optimize_pins.zip <10_optimize_pins.zip>`


.. only:: html

 .. rst-class:: sphx-glr-signature

    `Gallery generated by Sphinx-Gallery <https://sphinx-gallery.github.io>`_