.. DO NOT EDIT.
.. THIS FILE WAS AUTOMATICALLY GENERATED BY SPHINX-GALLERY.
.. TO MAKE CHANGES, EDIT THE SOURCE PYTHON FILE:
.. "auto_openfpga_config/configuration_chain.py"
.. LINE NUMBERS ARE GIVEN BELOW.

.. only:: html

    .. note::
        :class: sphx-glr-download-link-note

        :ref:`Go to the end <sphx_glr_download_auto_openfpga_config_configuration_chain.py>`
        to download the full example code.

.. rst-class:: sphx-glr-example-title

.. _sphx_glr_auto_openfpga_config_configuration_chain.py:


=========================================
Adding configuration chain to the fabric
=========================================

This example demonstate how to create a tile strcuture from
Verilog netlist obtained from OpenFPGA

.. image:: ../../../examples/OpenFPGA_config/_fpga_configuration_chain.svg
    :width: 500px
    :align: center

.. GENERATED FROM PYTHON SOURCE LINES 14-113

.. code-block:: Python


    import glob
    import logging
    import os
    import tempfile
    from itertools import chain

    import spydrnet as sdn
    from spydrnet_physical.util import OpenFPGA
    from spydrnet_physical.util import config_chain_simple
    from spydrnet_physical.util import FloorPlanViz
    from spydrnet_physical.util.shell import launch_shell

    logger = logging.getLogger("spydrnet_logs")
    sdn.enable_file_logging(LOG_LEVEL="INFO")


    def main():
        # Read verilog sources
        proj = "../homogeneous_fabric"
        source_files = glob.glob(f"{proj}/*_Verilog/lb/*.v")
        source_files += glob.glob(f"{proj}/*_Verilog/routing/*.v")
        source_files += glob.glob(f"{proj}/*_Verilog/sub_module/*.v")
        source_files += glob.glob(f"{proj}/*_Verilog/fpga_top.v")

        # Create OpenFPGA object
        fpga = OpenFPGA(grid=(4, 4), verilog_files=source_files)

        fpga.placement_creator.gridIO = True
        fpga.create_placement()

        # =========================
        # General netlist cleanup
        # =========================

        fpga.create_grid_clb_bus()
        fpga.create_grid_io_bus()
        fpga.create_sb_bus()
        fpga.create_cb_bus()

        fpga.remove_config_chain()
        fpga.remove_undriven_nets()

        # Convert top level independent nets to bus
        for i in chain(
            fpga.top_module.get_instances("grid_clb*"),
            fpga.top_module.get_instances("grid_io*"),
            fpga.top_module.get_instances("sb_*"),
        ):
            for p in filter(lambda x: True, i.reference.ports):
                if p.size > 1 and (i.check_all_scalar_connections(p)):
                    cable_list = []
                    for pin in p.pins[::-1]:
                        cable_list.append(i.pins[pin].wire.cable)
                    cable = fpga.top_module.combine_cables(f"{i.name}_{p.name}", cable_list)
                    cable.is_downto = False

        # fpga.create_grid_clb_feedthroughs()

        # ===============================
        # Add configuration chain
        # ===============================
        fpga.register_config_generator(config_chain_simple)
        fpga.add_configuration_scheme()
        fpga.config_creator.write_fabric_key("_fabric_key.xml")

        # ===============================
        # Simple Florrplan
        # ===============================
        next(fpga.top_module.get_ports("ccff_head")).properties["SIDE"] = "right"
        next(fpga.top_module.get_ports("ccff_head")).properties["OFFSET"] = 100

        next(fpga.top_module.get_ports("ccff_tail")).properties["SIDE"] = "right"
        next(fpga.top_module.get_ports("ccff_tail")).properties["OFFSET"] = 1250

        fpga.top_module.properties["WIDTH"] = 1500
        fpga.top_module.properties["HEIGHT"] = 1500

        # ===============================
        # Visualise configuration chain
        # ===============================
        fp = FloorPlanViz(fpga.top_module)
        fp.compose(filter_cables=(lambda x: "ccff" in x.name), skip_pins=False)
        dwg = fp.get_svg()
        dwg.saveas("_fpga_configuration_chain.svg", pretty=True, indent=4)

        # Save verilog netlist
        base_dir = ("..", "homogeneous_fabric", "_output_3")
        fpga.save_netlist("sb*", os.path.join(*base_dir, "routing"), skip_constraints=False)
        fpga.save_netlist("cb*", os.path.join(*base_dir, "routing"), skip_constraints=False)
        fpga.save_netlist("grid*", os.path.join(*base_dir, "lb"), skip_constraints=False)
        fpga.save_netlist(
            "*tile*", os.path.join(*base_dir, "tiles"), skip_constraints=False
        )
        fpga.save_netlist("fpga_top", os.path.join(*base_dir), skip_constraints=False)


    if __name__ == "__main__":
        main()


.. _sphx_glr_download_auto_openfpga_config_configuration_chain.py:

.. only:: html

  .. container:: sphx-glr-footer sphx-glr-footer-example

    .. container:: sphx-glr-download sphx-glr-download-jupyter

      :download:`Download Jupyter notebook: configuration_chain.ipynb <configuration_chain.ipynb>`

    .. container:: sphx-glr-download sphx-glr-download-python

      :download:`Download Python source code: configuration_chain.py <configuration_chain.py>`

    .. container:: sphx-glr-download sphx-glr-download-zip

      :download:`Download zipped: configuration_chain.zip <configuration_chain.zip>`


.. only:: html

 .. rst-class:: sphx-glr-signature

    `Gallery generated by Sphinx-Gallery <https://sphinx-gallery.github.io>`_