.. _sample_verilog_basic_hierarchy:

basic_hierarchy
=================

.. hdl-diagram:: ../../../spydrnet_physical/support_files/sample_verilog/basic_hierarchy.v
   :type: netlistsvg
   :align: center


.. literalinclude:: ../../../spydrnet_physical/support_files/sample_verilog/basic_hierarchy.v
   :language: verilog