.. _sample_verilog_grid_example:

grid_example
=================

.. hdl-diagram:: ../../../spydrnet_physical/support_files/sample_verilog/grid_example.v
   :type: netlistsvg
   :align: center


.. literalinclude:: ../../../spydrnet_physical/support_files/sample_verilog/grid_example.v
   :language: verilog