2.1. OpenFPGA architecture parsing

This example demonstrates the OpenFPGA_Arch class which parses the VPR and OpenFPGA Architecture file and provides logical information.

import os
import logging
import spydrnet as sdn
from spydrnet_physical.util import OpenFPGA_Arch

# Enable output logging
logger = logging.getLogger("spydrnet_logs")
sdn.enable_file_logging(LOG_LEVEL="INFO", filename="01_fpga_arch_parse")

# Read OpenFPGA and VPR architectue file
task_dir = ("..", "homogeneous_fabric", "FPGA44_Task")
vpr_arch = os.path.join(*task_dir, "arch", "k6_N10_tileable.xml")
openfpga_arch = os.path.join(*task_dir, "arch", "k6_N10_openfpga.xml")
fpga_arch = OpenFPGA_Arch(vpr_arch, openfpga_arch, layout="4x4")

# Print avaialble layouts and pb_types in the file
logger.info(fpga_arch.get_layouts())
logger.info(fpga_arch.pb_types)
# logger.info(fpga_arch.is_homogeneous())

2.1.1. Output

 INFO 01_fpga_arch_parse.py:26 (MainThread) - {'4x4': (6, 6)}
 INFO 01_fpga_arch_parse.py:27 (MainThread) - {'io': (1, 1), 'clb': (1, 1)}