Hide navigation sidebar

Hide table of contents sidebar

Toggle site navigation sidebar

SpyDrNet-Physical alpha documentation

Toggle table of contents sidebar

SpyDrNet-Physical alpha documentation

Users Content

Install
Tutorial
Toggle child pages in navigation
API Reference
Toggle child pages in navigation
- SpyDrNet-Physical API Summary
  Toggle child pages in navigation
  - Library
  - Bundle
  - Element
  - Definition
  - Instance
  - Cable
  - Wire
  - InnerPin
  - OuterPin
  - Pin
  - Port
- Visualization and Floorplanning
- Connectivity Pattern Generation
- OpenFPGA Transformations
  Toggle child pages in navigation
  - OpenFPGA Base
  - OpenFPGA Arch Parser
  - Routing Render
  - Tile-01
    Toggle child pages in navigation
  - Tile-02
  - Configuration Chain Pattern 01
  - Configuration Chain Pattern 01
  - SRAM Configuration Protocol
  - Initial Heterogeneous Placement
  - Bitstream Manager
- Utility Classes
Verilog Language Support
Sample verilog netlist
Physical Design for 4x4 FPGA
Examples
Toggle child pages in navigation

Developeres Content

Developers Guidelines
Regression Tests
Toggle child pages in navigation

Toggle table of contents sidebar

Top-Right-Tile¶

Bottom-left-Tile

Copyright © 2021, University of Utah | Built with Sphinx and @pradyunsg's Furo theme. | Show Source