Tile-01¶
This tiling method performance minimal modification in the OpenFPGA generated netlist. After performing base manipulation to convert wires to buses, this tiling scheme merges neighboring instances to form a structure like shown below. This scheme is biased toward the top and right side connections boxes and right-top side switch box, as it merges connection boxes on top and right and sb on the right-top corner for flat design.
The flat design of the merged module allows setting tighter timing constraints on all internal paths.
Detail of each Tile¶
Methods¶
- class spydrnet_physical.util.Tile01(grid, netlist, library, top_module)[source]¶
Methods:
Creates tiles
Merges given list of instances and updates width and height parameter
_get_width_height
_update_placement
Create main Tiles
Create Left Tiles
Create Right Tiles
Create Top Tiles
Create Bottom Tiles
Create top left tile
Create top right tile
Create bottom left tile
Create bottom right tile
- merge_and_update(instance_list, tile_name)[source]¶
Merges given list of instances and updates width and height parameter
- _main_tile()[source]¶
Create main Tiles
+-----+ | | +-------+ +---- ---+ | CBY | | SB | +-------+ +---- ---+ +---------------+ | | | | +-----+ | | +-----+ | | | | | CLB | | CBX | | | +-----+ | | +---------------+
- _left_tile()[source]¶
Create Left Tiles
+-----+ +-----+ | | | | | +--+ +-------+ +---+ +--+ | SB | | CBY | | SB | | +--+ +-------+ +---+ +--+ | | +--------------+ | | +-----+ | | +-----+ +-----+ | | +-----+ | | | | | | | CBX | | CLB | | CBX | +-----+ | | +-----+ | | +--------------+
- _right_tile()[source]¶
Create Right Tiles
+-----+ | | +-------+ +--+ | | CBY | | SB | +-------+ +--+ | +--------------+ | | | | +-----+ | | +-----+ | | | | | CLB | | CBX | | | +-----+ | | +--------------+
- _top_tile()[source]¶
Create Top Tiles
+-------+ +------------+ | CBY | | SB | +-------+ +---+ +--+ +--------------+ | | | | +-----+ | | +-----+ | | | | | CLB | | CBX | | | +-----+ | | +--------------+
- _bottom_tile()[source]¶
Create Bottom Tiles
+-----+ | | +-------+ +---+ +--+ | CBY | | SB | +-------+ +---+ +--+ +--------------+ | | | | +-----+ | | +-----+ | | | | | CLB | | CBX | | | +-----+ | | +-----+ +--------------+ | | +-------+ +---+ +--+ | CBY | | SB | +-------+ +------------+
- _top_left_tile()[source]¶
Create top left tile
+--------+ +-------+ +------------+ | SB | | CBX | | SB | | +--+ +-------+ +---+ +--+ | | +--------------+ | | +-----+ | | +-----+ +-----+ | | +-----+ | | | | | | | CBY | | CLB | | CBY | +-----+ | | +-----+ | | +--------------+
- _top_right_tile()[source]¶
Create top right tile
+------------+ +-------+ +---------+ | SB | | CBY | | SB | +---+ +--+ +-------+ +---+ | | | +--------------+ | | +-----+ | | +-----+ +-----+ | | +-----+ | | | | | | | CBX | | CLB | | CBX | +-----+ | | +-----+ | | +--------------+
- _bottom_left_tile()[source]¶
Create bottom left tile
+-----+ +-----+ | | | | | +--+ +-------+ +---+ +--+ | SB | | CBY | | SB | | | +--+ +-------+ +---+ +--+ | | +--------------+ | | +-----+ | | +-----+ +-----+ | | +-----+ | | | | | | | CBX | | CLB | | CBX | +-----+ | | +-----+ +-----+ | | +-----+ | | +--------------+ | | | +--+ +-------+ +---+ +--+ | SB | | CBY | | SB | +--------+ +-------+ +------------+