5.7. Adding Tie Cells on Floating Pins

THis example

Original grided netlist

After adding tie cells

from os import path
from pprint import pprint
import spydrnet as sdn
from spydrnet_physical.util import ConnectionPattern
import spydrnet_physical as sdnphy


# Verilog netlist
netlist = sdnphy.load_netlist_by_name('square_grid')
top_definition = netlist.top_instance.reference
top_definition.split_port("in")
top_definition.split_port("out")
top_definition.create_unconn_wires()
sdn.compose(netlist, '_square_grid_design.v', skip_constraints=True)

netlist = sdnphy.load_netlist_by_name('square_grid')
top_definition = netlist.top_instance.reference

# Pattern
p_manager = ConnectionPattern(4, 4)
fishbone_pattern = p_manager.get_fishbone(steps=2)
svg = p_manager.render_pattern(title="Merging option")
svg.saveas("_fishbone_pattern_tie_0.svg", pretty=True, indent=4)


def get_top_instance_name(x, y):
    if 0 in (x, y):
        return "top"
    return f"inst_1_{x}{y}"


fishbone_pattern.get_top_instance_name = get_top_instance_name
clk_port = top_definition.create_port("clk", direction=sdn.IN, pins=1)
clk_cable = top_definition.create_cable("clk", wires=1)
clk_cable.connect_port(clk_port)
fishbone_pattern.create_ft_ports(netlist, "clk", clk_cable)
fishbone_pattern.create_ft_connection(netlist, clk_cable)

portmap = fishbone_pattern.show_stats(netlist)
pprint(dict(portmap))
for module, ports in portmap.items():
    if module == "top":
        continue
    pprint(ports["in"])
    ports = [f"clk_{key}_in" for key, value in ports["in"].items() if value]
    ports = [next(netlist.get_ports(port)).pins[0] for port in ports]
    for instance in next(netlist.get_definitions(module)).references:
        print(f">>>>>>> {instance.name}", end=" ")
        print("" if any(
            [instance.pins[port].wire for port in ports]) else "Tie this")

# fishbone_pattern.print_instance_grid_map()
# fishbone_pattern.print_reference_grid_map(netlist)

top_definition.create_unconn_wires()
sdn.compose(netlist, '_tie_cell_added.v',
            skip_constraints=True,
            write_blackbox=True)

Output Netlist

//Generated from netlist by SpyDrNet
//netlist name: SDN_VERILOG_NETLIST_top
module top
(
    in,
    out,
    clk
);

    input [3:0]in;
    output [3:0]out;
    input clk;

    wire [3:0]in;
    wire [3:0]out;
    wire [3:0]row1;
    wire [3:0]row2;
    wire [3:0]row3;
    wire [3:0]row4;
    wire clk;
    wire [8:0]clk_ft;
    wire [79:0]unconn;

assign clk_ft[0] = clk;
    module1 inst_1_11
    (
        .in0(in[0]),
        .out0(row1[0]),
        .clk_left_in(unconn[1]),
        .clk_right_in(clk_ft[3]),
        .clk_bottom_in(unconn[2]),
        .clk_top_out(unconn[3]),
        .clk_right_out(unconn[4]),
        .clk_left_out(unconn[5])
    );
    module1 inst_1_21
    (
        .in0(row1[0]),
        .out0(row1[1]),
        .clk_left_in(unconn[6]),
        .clk_right_in(unconn[7]),
        .clk_bottom_in(clk_ft[0]),
        .clk_top_out(clk_ft[4]),
        .clk_right_out(clk_ft[1]),
        .clk_left_out(clk_ft[3])
    );
    module1 inst_1_31
    (
        .in0(row1[1]),
        .out0(row1[2]),
        .clk_left_in(clk_ft[1]),
        .clk_right_in(unconn[8]),
        .clk_bottom_in(unconn[9]),
        .clk_top_out(unconn[10]),
        .clk_right_out(clk_ft[2]),
        .clk_left_out(unconn[11])
    );
    module1 inst_1_41
    (
        .in0(row1[2]),
        .out0(out[0]),
        .clk_left_in(clk_ft[2]),
        .clk_right_in(unconn[12]),
        .clk_bottom_in(unconn[13]),
        .clk_top_out(unconn[14]),
        .clk_right_out(unconn[15]),
        .clk_left_out(unconn[16])
    );
    module1 inst_1_12
    (
        .in0(in[1]),
        .out0(row2[0]),
        .clk_left_in(unconn[17]),
        .clk_right_in(unconn[18]),
        .clk_bottom_in(unconn[19]),
        .clk_top_out(unconn[20]),
        .clk_right_out(unconn[21]),
        .clk_left_out(unconn[22])
    );
    module1 inst_1_22
    (
        .in0(row2[0]),
        .out0(row2[1]),
        .clk_left_in(unconn[23]),
        .clk_right_in(unconn[24]),
        .clk_bottom_in(clk_ft[4]),
        .clk_top_out(clk_ft[5]),
        .clk_right_out(unconn[25]),
        .clk_left_out(unconn[26])
    );
    module1 inst_1_32
    (
        .in0(row2[1]),
        .out0(row2[2]),
        .clk_left_in(unconn[27]),
        .clk_right_in(unconn[28]),
        .clk_bottom_in(unconn[29]),
        .clk_top_out(unconn[30]),
        .clk_right_out(unconn[31]),
        .clk_left_out(unconn[32])
    );
    module1 inst_1_42
    (
        .in0(row2[2]),
        .out0(out[1]),
        .clk_left_in(unconn[33]),
        .clk_right_in(unconn[34]),
        .clk_bottom_in(unconn[35]),
        .clk_top_out(unconn[36]),
        .clk_right_out(unconn[37]),
        .clk_left_out(unconn[38])
    );
    module1 inst_1_13
    (
        .in0(in[2]),
        .out0(row3[0]),
        .clk_left_in(unconn[39]),
        .clk_right_in(clk_ft[8]),
        .clk_bottom_in(unconn[40]),
        .clk_top_out(unconn[41]),
        .clk_right_out(unconn[42]),
        .clk_left_out(unconn[43])
    );
    module1 inst_1_23
    (
        .in0(row3[0]),
        .out0(row3[1]),
        .clk_left_in(unconn[44]),
        .clk_right_in(unconn[45]),
        .clk_bottom_in(clk_ft[5]),
        .clk_top_out(unconn[46]),
        .clk_right_out(clk_ft[6]),
        .clk_left_out(clk_ft[8])
    );
    module1 inst_1_33
    (
        .in0(row3[1]),
        .out0(row3[2]),
        .clk_left_in(clk_ft[6]),
        .clk_right_in(unconn[47]),
        .clk_bottom_in(unconn[48]),
        .clk_top_out(unconn[49]),
        .clk_right_out(clk_ft[7]),
        .clk_left_out(unconn[50])
    );
    module1 inst_1_43
    (
        .in0(row3[2]),
        .out0(out[2]),
        .clk_left_in(clk_ft[7]),
        .clk_right_in(unconn[51]),
        .clk_bottom_in(unconn[52]),
        .clk_top_out(unconn[53]),
        .clk_right_out(unconn[54]),
        .clk_left_out(unconn[55])
    );
    module1 inst_1_14
    (
        .in0(in[3]),
        .out0(row4[0]),
        .clk_left_in(unconn[56]),
        .clk_right_in(unconn[57]),
        .clk_bottom_in(unconn[58]),
        .clk_top_out(unconn[59]),
        .clk_right_out(unconn[60]),
        .clk_left_out(unconn[61])
    );
    module1 inst_1_24
    (
        .in0(row4[0]),
        .out0(row4[1]),
        .clk_left_in(unconn[62]),
        .clk_right_in(unconn[63]),
        .clk_bottom_in(unconn[64]),
        .clk_top_out(unconn[65]),
        .clk_right_out(unconn[66]),
        .clk_left_out(unconn[67])
    );
    module1 inst_1_34
    (
        .in0(row4[1]),
        .out0(row4[2]),
        .clk_left_in(unconn[68]),
        .clk_right_in(unconn[69]),
        .clk_bottom_in(unconn[70]),
        .clk_top_out(unconn[71]),
        .clk_right_out(unconn[72]),
        .clk_left_out(unconn[73])
    );
    module1 inst_1_44
    (
        .in0(row4[2]),
        .out0(out[3]),
        .clk_left_in(unconn[74]),
        .clk_right_in(unconn[75]),
        .clk_bottom_in(unconn[76]),
        .clk_top_out(unconn[77]),
        .clk_right_out(unconn[78]),
        .clk_left_out(unconn[79])
    );
endmodule

module module1
(
    in0,
    out0,
    clk_left_in,
    clk_right_in,
    clk_bottom_in,
    clk_top_out,
    clk_right_out,
    clk_left_out
);

    input in0;
    output out0;
    input clk_left_in;
    input clk_right_in;
    input clk_bottom_in;
    output clk_top_out;
    output clk_right_out;
    output clk_left_out;

    wire in0;
    wire clk;
    wire out0;
    wire clk_left_in;
    wire clk_right_in;
    wire clk_bottom_in;
    wire clk_top_out;
    wire clk_right_out;
    wire clk_left_out;

assign clk_right_in = clk_left_in;
assign clk_bottom_in = clk_right_in;
assign clk = clk_bottom_in;
assign clk_top_out = clk_right_out;
assign clk_right_out = clk_left_out;
assign clk_left_out = clk;
endmodule