OpenFPGA Base

class spydrnet_physical.util.OpenFPGA(grid, netlist=None, verilog_files=None, library='work', top_module='fpga_top', arch_xml=None)

This is top-level clas of OpenFPGa which provides methods for different generic netlist restructuring

Attributes:

SC_HEIGHT
CPP
GLOBAL_SCALE
SC_GRID
netlist	Returns library
library	Returns library
top_module	Returns top_module

Methods:

__init__	Init class with OpenFPGA netlist
register_tile_generator	This registers the tile generator class to OpenFPGA base class
register_config_generator	This registers the tile generator class to OpenFPGA base class
register_placement_creator	This registers the tile generator class to OpenFPGA base class
create_tiles	proxy function to create_tiles method of tile_creator class
add_configuration_scheme	proxy function to create_tiles method of tile_creator class
create_placement	Proxy fucntion to add placement and shaping information to each instance
place_pins	This adds pin placment nforamtion to tile instances
render_floorplan	This method runs the fpga render class to assign shape and location to each module instance
get_custom_boundary
get_cross_shape_boundary
save_shaping_data	Save the shaping data
show_placement_data	This shows the placement data of each instance on the screen
show_utilization_data	Show the utilization of the modules
design_instance_map	Returns instance current netlist instance map
design_top_stat	Get statistics of the top module
remove_direct_interc	Removes direct interconnects from the OpenFPGA netlist
merge_all_grid_ios	This method creates the group of grid_io and neighbouring connection_box whichcna be merge.
remove_config_chain	Remove configuration chain from design
remove_undriven_nets	Removes undriven/floating nets from the top level
create_grid_io_bus	Convert grid_io Input/Output pins to bus structure
create_grid_clb_bus	Convert grid_clb Input/Output pins to bus structure
create_sb_bus	Convert sb Input pins to bus structure
create_cb_bus	Convert cb Input pins to bus structure
create_grid_clb_feedthroughs	Creates feedthrough for grid_clb outputs, to convert digonal connections to horizontal and vertical
clear_written_modules
write_include_file
save_netlist	Save verilog files
load_grid
get_top_instance	This method generates the grid instance information given the cordinate points
fix_grid_pin_names	This method is used to fix the pin names on the grid modules
annotate_area_information	This method annotated the area infomration on each definition of the top level module
hierarchy
update_module_label	Adde area information to label
get_overutils_styles	Analyzes utilisation of each module and returns CSS string to highlight in the SVG

__init__(grid, netlist=None, verilog_files=None, library='work', top_module='fpga_top', arch_xml=None)

Init class with OpenFPGA netlist

Parameters

• grid (int, int) – Size of the FPGA grid

• netlist (sdn.netlist) – Pass OpenFPGA core netlist

• library (str) – library name

• top_module (str) – top_module name

property netlist

Returns library

property library

Returns library

property top_module: spydrnet.ir.Definition

Returns top_module

register_tile_generator(cls, *args, **kwargs)

This registers the tile generator class to OpenFPGA base class

register_config_generator(cls, *args, **kwargs)

This registers the tile generator class to OpenFPGA base class

register_placement_creator(cls, *args, **kwargs)

This registers the tile generator class to OpenFPGA base class

create_tiles()

proxy function to create_tiles method of tile_creator class

add_configuration_scheme()

proxy function to create_tiles method of tile_creator class

create_placement(*args, **kwargs)

Proxy fucntion to add placement and shaping information to each instance

place_pins()

This adds pin placment nforamtion to tile instances

render_floorplan()

This method runs the fpga render class to assign shape and location to each module instance

save_shaping_data(pattern='*', scale=None, filename=None)

Save the shaping data

show_placement_data(pattern='*', filename=None)

This shows the placement data of each instance on the screen

show_utilization_data(pattern='*', filename=None)

Show the utilization of the modules

design_instance_map(pattern='*', quiet=False)

Returns instance current netlist instance map

design_top_stat(pattern='*', quiet=False, filename=None, function=())

Get statistics of the top module

remove_direct_interc()

Removes direct interconnects from the OpenFPGA netlist

merge_all_grid_ios()

This method creates the group of grid_io and neighbouring connection_box whichcna be merge.

Variable cb_list, grid_io_list first creates the list of instances on the periphery of the FPGA, starting from the left bottom corner and going clockwise

merge_list is a dictionary which creates the group of instances for different unique pairs of the IO and CB blocks

remove_config_chain(name='ccff_')

Remove configuration chain from design

remove_undriven_nets(pattern='*')

Removes undriven/floating nets from the top level

the net name with undriven keyword in the name is considered as floating nets

create_grid_io_bus(inpad='inpad', outpad='outpad', sort_pins=None)

Convert grid_io Input/Output pins to bus structure

# Input Pins
right_width_0_height_0_subtile_*__pin_inpad_0_    -> io_right_in
left_width_0_height_0_subtile_*__pin_inpad_0_     -> io_left_in
top_width_0_height_0_subtile_*__pin_inpad_0_      -> io_top_in
bottom_width_0_height_0_subtile_*__pin_inpad_0_   -> io_bottom_in

# Output Pins
right_width_0_height_0_subtile_*__pin_outpad_0_   -> io_right_out
left_width_0_height_0_subtile_*__pin_outpad_0_    -> io_left_out
top_width_0_height_0_subtile_*__pin_outpad_0_     -> io_top_out
bottom_width_0_height_0_subtile_*__pin_outpad_0_  -> io_bottom_out

create_grid_clb_bus(pins=None, grid_module='grid_clb')

Convert grid_clb Input/Output pins to bus structure

# Input Pins
right_width_0_height_0_subtile_*__pin_I_0_    -> grid_right_in
left_width_0_height_0_subtile_*__pin_I_0_     -> grid_left_in
top_width_0_height_0_subtile_*__pin_I_0_      -> grid_top_in
bottom_width_0_height_0_subtile_*__pin_I_0_   -> grid_bottom_in

# Output Pins
right_width_0_height_0_subtile_*__pin_O_0_    -> grid_right_out
left_width_0_height_0_subtile_*__pin_O_0_     -> grid_left_out
top_width_0_height_0_subtile_*__pin_O_0_      -> grid_top_out
bottom_width_0_height_0_subtile_*__pin_O_0_   -> grid_bottom_out

create_sb_bus(pins=None)

Convert sb Input pins to bus structure

# Input Pins
top_left_grid_right_width_0_height_0_subtile_*__pin_O_*_      -> sb_top_l_in
top_right_grid_left_width_0_height_0_subtile_*__pin_O_*_      -> sb_top_r_in
bottom_left_grid_right_width_0_height_0_subtile_*__pin_O_*_   -> sb_bottom_l_in
bottom_right_grid_left_width_0_height_0_subtile_*__pin_O_*_   -> sb_bottom_r_in

left_top_grid_bottom_width_0_height_0_subtile_*__pin_O_*_     -> sb_left_t_in
left_bottom_grid_top_width_0_height_0_subtile_*__pin_O_*_     -> sb_left_b_in
right_top_grid_bottom_width_0_height_0_subtile_*__pin_O_*_    -> sb_right_t_in
right_bottom_grid_top_width_0_height_0_subtile_*__pin_O_*_    -> sb_right_b_in

create_cb_bus(pins=None)

Convert cb Input pins to bus structure

right_grid_left_width_0_height_0_subtile_*__pin_I_*_      -> grid_right_in
left_grid_right_width_0_height_0_subtile_*__pin_I_*_      -> grid_left_in
top_grid_bottom_width_0_height_0_subtile_*__pin_I_*_      -> grid_top_in
bottom_grid_top_width_0_height_0_subtile_*__pin_I_*_      -> grid_bottom_in

right_grid_left_width_0_height_0_subtile_*__pin_outpad_*_ -> grid_right_in
left_grid_right_width_0_height_0_subtile_*__pin_outpad_*_ -> grid_left_in
top_grid_bottom_width_0_height_0_subtile_*__pin_outpad_*_ -> grid_top_in
bottom_grid_top_width_0_height_0_subtile_*__pin_outpad_*_ -> grid_bottom_in

create_grid_clb_feedthroughs()

Creates feedthrough for grid_clb outputs, to convert digonal connections to horizontal and vertical

grid_clb output on each side is feedthrough from connection box as shown in the following example (onle left side feedthroughs are shown)

+-----+                       +-----+
|     |                       |     |
|     +--+                    |     +--+
| SB     |                    | SB     |
|     +-++                    |     +--+
|     | |                     |     |
+-----+ |                     +--+--+
        |  +------               |       +------
+-----+ |  |                  +-----+    |
|     | |  |                  |  |  |    |
|     | +--+ CLB              |  +-------+ CLB
| CBX | |  |                  |  |  |    |
+-----+ |  |                  +-----+    |
        |  |                     |       |
+-----+ |  +------            +--+--+    +------
|     | |                     |     |
|     +-++                    |     +--+
| SB     |                    | SB     |
|     +--+                    |     +--+
|     |                       |     |
+-----+                       +-----+
Before                After feedthrough creations

save_netlist(patten='*', location='.', sort_print=False, skip_constraints=True, sort_cables=False, sort_instances=False, sort_ports=False, write_blackbox=True)

Save verilog files

get_top_instance(x, y)

This method generates the grid instance information given the cordinate points

fix_grid_pin_names(regex='.*__pin_(.*)_0_', module='grid_*', name_map=None)

This method is used to fix the pin names on the grid modules

Parameters

regex (str) – Regex string used to extract the name of the port

annotate_area_information(filename, skipline=0)

This method annotated the area infomration on each definition of the top level module

update_module_label(get_label=None)

Adde area information to label

get_overutils_styles(target=0.95, color='#D60B00')

Analyzes utilisation of each module and returns CSS string to highlight in the SVG