2.9. Renaming Homogeneous FPGA Modules

Demonstrates how to rename FPGA modules

from glob import glob
import logging

import spydrnet as sdn
from spydrnet_physical.util import OpenFPGA

logger = logging.getLogger('spydrnet_logs')
sdn.enable_file_logging(LOG_LEVEL='INFO')


proj = "../homogeneous_fabric"
source_files = glob(f'{proj}/*_Verilog/lb/*.v')
source_files += glob(f'{proj}/*_Verilog/routing/*.v')
source_files += glob(f'{proj}/*_Verilog/sub_module/*.v')
source_files += glob(f'{proj}/*_Verilog/fpga_top.v')

# Create OpenFPGA object
fpga = OpenFPGA(grid=(4, 4), verilog_files=source_files)
fpga.design_top_stat(filename="_before_rename.txt")

# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
#           Renaming Module
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
rename_modules_map = {
    "grid_clb": "logic_block",
    "cbx_1__1_": "h_conn",
    "cby_1__1_": "v_conn"
}
for each_module, new_name in rename_modules_map.items():
    next(fpga.top_module.get_definitions(each_module)).name = new_name

fpga.design_top_stat(filename="_after_rename.txt")

Output

before_rename

= = = = = = = = = = = = = = = = = = = = 
= = = = = =  DESIGN STATS = = = = = = = 
= = = = = = = = = = = = = = = = = = = = 
    top_module : fpga_top
    definitions: 20
    instances  : 97
= = = = = = = = = = = = = = = = = = = = 
          References    count
- - - - - - - - - - - - - - - - - - - - 
           cbx_1__0_        4
           cbx_1__1_       12
           cbx_1__4_        4
           cby_0__1_        4
           cby_1__1_       12
           cby_4__1_        4
            grid_clb       16
      grid_io_bottom        4
        grid_io_left        4
       grid_io_right        4
         grid_io_top        4
            sb_0__0_        1
            sb_0__1_        3
            sb_0__4_        1
            sb_1__0_        3
            sb_1__1_        9
            sb_1__4_        3
            sb_4__0_        1
            sb_4__1_        3
            sb_4__4_        1

after_rename

= = = = = = = = = = = = = = = = = = = = 
= = = = = =  DESIGN STATS = = = = = = = 
= = = = = = = = = = = = = = = = = = = = 
    top_module : fpga_top
    definitions: 20
    instances  : 97
= = = = = = = = = = = = = = = = = = = = 
          References    count
- - - - - - - - - - - - - - - - - - - - 
           cbx_1__0_        4
           cbx_1__4_        4
           cby_0__1_        4
           cby_4__1_        4
      grid_io_bottom        4
        grid_io_left        4
       grid_io_right        4
         grid_io_top        4
              h_conn       12
         logic_block       16
            sb_0__0_        1
            sb_0__1_        3
            sb_0__4_        1
            sb_1__0_        3
            sb_1__1_        9
            sb_1__4_        3
            sb_4__0_        1
            sb_4__1_        3
            sb_4__4_        1
              v_conn       12