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SpyDrNet-Physical alpha documentation
SpyDrNet-Physical alpha documentation

Users Content

  • Install
  • Tutorial
    • Example
    • Shell Interface
    • Visualization
  • API Reference
    • SpyDrNet-Physical API Summary
      • Library
      • Bundle
      • Element
      • Definition
      • Instance
      • Cable
      • Wire
      • InnerPin
      • OuterPin
      • Pin
      • Port
    • Visualization and Floorplanning
    • Connectivity Pattern Generation
    • OpenFPGA Transformations
      • OpenFPGA Base
      • OpenFPGA Arch Parser
      • Routing Render
      • Tile-01
        • Tile
        • Left-Tile
        • Right-Tile
        • Top-Tile
        • Bottom-Tile
        • Top-left-Tile
        • Top-Right-Tile
        • Bottom-left-Tile
        • Bottom-Right-Tile
      • Tile-02
      • Configuration Chain Pattern 01
      • Configuration Chain Pattern 01
      • SRAM Configuration Protocol
      • Initial Heterogeneous Placement
      • Bitstream Manager
    • Utility Classes
  • Verilog Language Support
  • Sample verilog netlist
  • Physical Design for 4x4 FPGA
  • Examples
    • 1. Basic Restructuring Examples
      • 1.1. Display Netlist Information Functions
      • 1.2. Visualise Hierarchical Netlist (SVG/Interactive)
      • 1.3. Generating feedthrough from multiple instances
      • 1.4. Combined definitions pins
      • 1.5. Combined independent nets
      • 1.6. Logging and debuging
      • 1.7. Buffering net
      • 1.8. Grouping ungrouping cells
      • 1.9. Merging two instances in the design
      • 1.10. Generating feedthrough from single instance
    • 2. OpenFPGA Basic Examples
      • 2.1. OpenFPGA architecture parsing
      • 2.2. FPGA layout grid generation
      • 2.3. Render FPGA Basic Elements
      • 2.4. RenderFPGA Pre Generation Grid
      • 2.5. FPGA Instance to Layout mapping
      • 2.6. Grid Floorplan Generator
      • 2.7. Optimizing module pins
      • 2.8. Represetes IO Sequence in OpenFPGA Engine
      • 2.9. Renaming Homogeneous FPGA Modules
    • 3. Module Rendering Examples
      • 3.1. Demonstrate how to render basic floorplan
      • 3.2. Placement aware instace merge operation
      • 3.3. Rendering Switch and Connection Boxes
      • 3.4. Rendering Switch and Connection Boxes
    • 4. Floorplanning Examples
      • 4.1. Auto floorplan homogeneous design
      • 4.2. Dimension based floorplanning
      • 4.3. Utilisation based floorplanning
      • 4.4. Heterogeneous Design Placement
      • 4.5. Heterogeneous Floorplan Adjustment
      • 4.6. Heterogeneous Floorplan Adjustment
    • 5. Clock Tree Embedding
      • 5.1. Connection Pattern Generation
      • 5.2. Create H-Tree Connectivity pattern
      • 5.3. Create Hybrid Connectivity Pattern
      • 5.4. Create Clock Tree Embedding
      • 5.5. Create Clock Tree Embedding
      • 5.6. Two layer H-Tree insertion in 4x4 FPGA
      • 5.7. Adding Tie Cells on Floating Pins
      • 5.8. Create Reset Feedthrough in fpga_top
      • 5.9. Clock tree insertion Example Architecture 1
      • 5.10. Clock tree insertion Example Architecture 2
      • 5.11. Clock tree insertion Example Architecture 3
      • 5.12. Clock tree insertion Example Architecture 3
      • 5.13. Grouping ungrouping cells
    • 6. Partition Examples
      • 6.1. Netlist to graph (networkx)
      • 6.2. Logical/Pre-techmapped Partition Conn Box 01
      • 6.3. Physical/Techmapped Partition Conn Box 02
      • 6.4. Partition Conn Box 02 - Simplified
      • 6.5. Split CBs and SBs across fabric
      • 6.6. Generic Tiling Part02 - Creating tile
      • 6.7. Generic Tiling Part02 - Creating tile
      • 6.8. Floorplanning Classic Tiles
      • 6.9. Generating and Floorplanning Area-optimized FPGA Tiles
      • 6.10. Unified routing tile structure
      • 6.11. Tile02 - Area optimized version with higher regularity
      • 6.12. Implementing memeory bank protocol on Tile02
      • 6.13. Floorplanning Classic Tiles for hetergeneous design
      • 6.14. Floorplanning Classic Tiles for hetergeneous design
      • 6.15. Partitions Experimentation
    • 7. Configuration Chain
      • 7.1. Create memory bank pin placement and connection
      • 7.2. Fabric key generation for homogeneous fabric
      • 7.3. Adding configuration chain to the fabric
      • 7.4. Extract configuration chain order

Developeres Content

  • Developers Guidelines
  • Regression Tests
    • Library - Unit tests
    • Element - Unit tests
    • Definition - Unit tests
    • Instance - Unit tests
    • Cable - Unit tests
    • Wire - Unit tests
    • Port - Unit tests
    • Pin - Unit tests
    • OuterPin - Unit tests
    • InnerPin - Unit tests

Sample verilog netlist¶

Basic netlist¶

basic_hierarchy

Fig. 2 basic_hierarchy¶

nested_hierarchy

Fig. 3 nested_hierarchy¶

Multi-instantiated design¶

grid_example

Fig. 4 grid_example¶

square_grid

Fig. 5 square_grid¶

Homogeneous FPGA outline¶

Heterogeneous FPGA outline¶

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Physical Design for 4x4 FPGA
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Verilog Language Support
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Contents
  • Sample verilog netlist
    • Basic netlist
    • Multi-instantiated design
    • Homogeneous FPGA outline
    • Heterogeneous FPGA outline