2.2. FPGA layout grid generation

This class generates the 2D matrix of the FPGA grid.

layout section of Architecture file

Expected Output:

_complete_fpga_grid This prints complete logic block grid, if the logic block has width or height larger than a unit LB width it is represeted by arrows (left and top arrows only)

Grid

  EMPTY      io_top     io_top     io_top     io_top     EMPTY    
 io_left       ↑         clb        clb        clb      io_right  
 io_left       ↑         clb        clb        clb      io_right  
 io_left       ↑         clb        clb        clb      io_right  
 io_left      mcu        clb        clb        clb      io_right  
  EMPTY    io_bottom  io_bottom  io_bottom  io_bottom    EMPTY    

Full Grid

  EMPTY      EMPTY      io_top     EMPTY      io_top     EMPTY      io_top     EMPTY      io_top     EMPTY      EMPTY    
  EMPTY        sb        cby         sb        cby         sb        cby         sb        cby         sb       EMPTY    
 io_left      cbx         ↑         cbx        clb        cbx        clb        cbx        clb        cbx      io_right  
  EMPTY        sb         ↑          sb        cby         sb        cby         sb        cby         sb       EMPTY    
 io_left      cbx         ↑         cbx        clb        cbx        clb        cbx        clb        cbx      io_right  
  EMPTY        sb         ↑          sb        cby         sb        cby         sb        cby         sb       EMPTY    
 io_left      cbx         ↑         cbx        clb        cbx        clb        cbx        clb        cbx      io_right  
  EMPTY        sb         ↑          sb        cby         sb        cby         sb        cby         sb       EMPTY    
 io_left      cbx        mcu        cbx        clb        cbx        clb        cbx        clb        cbx      io_right  
  EMPTY        sb        cby         sb        cby         sb        cby         sb        cby         sb       EMPTY    
  EMPTY      EMPTY    io_bottom    EMPTY    io_bottom    EMPTY    io_bottom    EMPTY    io_bottom    EMPTY      EMPTY    

_complete_grid_metrics

[    EMPTY 0 5     ][    io_top 1 5    ][    io_top 2 5    ][    io_top 3 5    ][    io_top 4 5    ][    EMPTY 5 5     ]
[   io_left 0 4    ][     mcu 1 1      ][     clb 2 4      ][     clb 3 4      ][     clb 4 4      ][   io_right 5 4   ]
[   io_left 0 3    ][     mcu 1 1      ][     clb 2 3      ][     clb 3 3      ][     clb 4 3      ][   io_right 5 3   ]
[   io_left 0 2    ][     mcu 1 1      ][     clb 2 2      ][     clb 3 2      ][     clb 4 2      ][   io_right 5 2   ]
[   io_left 0 1    ][     mcu 1 1      ][     clb 2 1      ][     clb 3 1      ][     clb 4 1      ][   io_right 5 1   ]
[    EMPTY 0 0     ][  io_bottom 1 0   ][  io_bottom 2 0   ][  io_bottom 3 0   ][  io_bottom 4 0   ][    EMPTY 5 0     ]

_complete_metrics

    EMPTY         EMPTY      io_top_1__5_     EMPTY      io_top_2__5_     EMPTY      io_top_3__5_     EMPTY      io_top_4__5_     EMPTY         EMPTY     
    EMPTY        sb_0__4_     cbx_1__4_      sb_1__4_     cbx_2__4_      sb_2__4_     cbx_3__4_      sb_3__4_     cbx_4__4_      sb_4__4_       EMPTY     
 io_left_0__4_   cby_0__4_     mcu_1__1_     cby_1__4_     clb_2__4_     cby_2__4_     clb_3__4_     cby_3__4_     clb_4__4_     cby_4__4_    io_right_5__4_ 
    EMPTY        sb_0__3_     mcu_1__1_      sb_1__3_     cbx_2__3_      sb_2__3_     cbx_3__3_      sb_3__3_     cbx_4__3_      sb_4__3_       EMPTY     
 io_left_0__3_   cby_0__3_     mcu_1__1_     cby_1__3_     clb_2__3_     cby_2__3_     clb_3__3_     cby_3__3_     clb_4__3_     cby_4__3_    io_right_5__3_ 
    EMPTY        sb_0__2_     mcu_1__1_      sb_1__2_     cbx_2__2_      sb_2__2_     cbx_3__2_      sb_3__2_     cbx_4__2_      sb_4__2_       EMPTY     
 io_left_0__2_   cby_0__2_     mcu_1__1_     cby_1__2_     clb_2__2_     cby_2__2_     clb_3__2_     cby_3__2_     clb_4__2_     cby_4__2_    io_right_5__2_ 
    EMPTY        sb_0__1_     mcu_1__1_      sb_1__1_     cbx_2__1_      sb_2__1_     cbx_3__1_      sb_3__1_     cbx_4__1_      sb_4__1_       EMPTY     
 io_left_0__1_   cby_0__1_     mcu_1__1_     cby_1__1_     clb_2__1_     cby_2__1_     clb_3__1_     cby_3__1_     clb_4__1_     cby_4__1_    io_right_5__1_ 
    EMPTY        sb_0__0_     cbx_1__0_      sb_1__0_     cbx_2__0_      sb_2__0_     cbx_3__0_      sb_3__0_     cbx_4__0_      sb_4__0_       EMPTY     
    EMPTY         EMPTY      io_bottom_1__0_     EMPTY      io_bottom_2__0_     EMPTY      io_bottom_3__0_     EMPTY      io_bottom_4__0_     EMPTY         EMPTY     

import logging

import spydrnet as sdn
from spydrnet_physical.util import FPGAGridGen

logger = logging.getLogger("spydrnet_logs")
sdn.enable_file_logging(LOG_LEVEL="INFO")


def main():
    """
    Main method
    """
    fpga = FPGAGridGen(
        design_name="example_design",
        arch_file="../support_files/vpr_arch_render_demo.xml",
        release_root="_release",
        layout="small",
    )
    fpga.enumerate_grid()
    # Print CLB Grid
    output = fpga.print_grid()

    # grid_output
    with open("_fpga_grid.txt", "w", encoding="UTF-8") as fp:
        fp.write(output)

    # full grid_output
    output = fpga.print_grid(grid="full_grid")
    with open("_fpga_full_grid.txt", "w", encoding="UTF-8") as fp:
        fp.write(output)

    # Complete Matrics
    with open("_complete_grid_metrics.txt", "w", encoding="UTF-8") as fp:
        for y in range(fpga.height - 1, -1, -1):
            for x in range(fpga.width):
                fp.write(f"[{' '.join(map(str, fpga.get_block(x, y))):^18}]")
            fp.write("\n")

    # Complete metrics
    with open("_complete_metrics.txt", "w", encoding="UTF-8") as fp:
        for y in range(2 * (fpga.height - 1), -1, -1):
            for x in range((fpga.width * 2) - 1):
                fp.write(f" {fpga.get_top_instance(x, y):^12} ")
            fp.write("\n")


if __name__ == "__main__":
    main()